1. Technical Field
The present invention relates to a test apparatus and an electronic device. More particularly, the present invention relates to a test apparatus for testing a device under test and an electronic device including therein a test circuit for testing a circuit under test.
2. Related Art
A test apparatus is known which tests a device under test (DUT) such as a semiconductor. The test apparatus supplies a test signal having a predetermined logical pattern to the DUT, detects a signal output from the DUT in response to the supplied test signal, and compares tie detected signal with an expected value, to judge whether the DUT is acceptable.
The test apparatus includes therein a pattern generator for sequentially generating a test pattern and a test signal output section for outputting a test signal having a logical pattern corresponding to the test pattern. The pattern generator sequentially reads an instruction from sequence data (a test instruction sequence) stored on a memory, and executes the read instruction. The pattern generator then reads from the memory pattern data corresponding to the executed instruction, and sequentially outputs the read pattern data as the test pattern. In this way, the test apparatus can supply the test signal having a predetermined logical pattern to the DUT.
The pattern generator has been capable of executing a test instruction to receive a result of comparing tie output signal from the DUT with the expected value and determine a next operation based on the received comparison result, as disclosed in Unexamined Japanese Patent Application Publications No. 2004-264047 and No. H07-73700, for example. However, the pattern generator has difficulties in stocking the results of a plurality of tests conducted on the DUT, so as to generate different test patterns for subsequent tests with reference to the results of the tests or evaluate the DUT based on the results of the tests.